The present invention relates generally to semiconductor device processing and, more particularly, to a method for forming a semiconductor device by uniformly etching dual, pre-doped polysilicon regions of the device.
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices has been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as P-channel MOS (PMOS), N-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors, etc. Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in a MOS transistor, an active device generally includes a source and drain region, as well as a gate electrode for modulating current between the source and drain regions.
One important aspect of the formation of such devices, or portions thereof, relates to various photolithography and etching processes. In photolithography, a wafer substrate is coated with a light-sensitive material known as photoresist. Next, the wafer is exposed to light, wherein the light striking the wafer is passed through a mask plate. This mask plate defines the desired features to be printed on the substrate. After exposure, the resist-coated wafer substrate is developed. The desired features as defined on the mask are then retained on the photoresist-coated substrate, while unexposed areas of resist are washed away. The wafer having the desired features defined is thereafter subjected to etching. Depending upon the production process, the etching may either be a wet etch in which liquid chemicals are used to remove wafer material or a dry etch in which wafer material is subjected to a radio frequency (RF) induced plasma. One particular concern relating to the etching process is maintaining control over the etching of the features, notably in the gate electrode region of the MOS transistor.
More specifically, one of the challenges encountered during the gate etch process of submicron technologies is the control of the etch profile. In many modern submicron processes, the gate electrode is comprised of a composite of layers of materials stacked on top of one another, and is thus commonly referred to as a xe2x80x9cgate stack.xe2x80x9d In an exemplary process, a CMOS transistor may have a gate stack including a 1000 angstrom (xc3x85) layer of tungsten (W), while a 500 xc3x85 of titanium nitride (TiN) provides a sheet resistance as low as 3 xcexa9fxe2x96xa1 (ohms per square), and a higher breakdown voltage for the gate oxide.
A commonly used gate stack is amorphous silicon (a-Si) or polysilicon (poly-Si) on top of a thin gate oxide. The a-Si or poly-Si is typically doped with N-type carriers for NMOS or with P-type carriers for PMOS to obtain asymmetry threshold voltage between N-channel and P-channel devices for a CMOS device. As the technologies evolve, the dimensions of integrated circuits shrink. In turn, as the IC dimensions get smaller, a thinner gate oxide is needed to maintain a level of gate capacitance for the performance of the IC devices. To avoid increasing the capacitance above the desired level, it is thus necessary to maintain a high conductivity in the a-Si or poly-Si to prevent the depletion of carriers in the gate region. This depletion of carriers tends to make the a-Si or poly-Si appear as an additional xe2x80x9coxide thicknessxe2x80x9d contributing series capacitance component that tends to lower the overall gate capacitance.
For an exemplary process having a 100 xc3x85 oxide layer, if the gate stack contributes 5 xc3x85 of xe2x80x9coxide thickness,xe2x80x9d the capacitance change would be about 5% (assuming other parameters are held constant). However, if a process has a 30 xc3x85 gate oxide layer, given a 5 xc3x85 change in thickness due to the oxide, the gate capacitance would change by about 20%. Therefore, the N-type and P-type doses required for the a-Si or poly-Si gate stack may be heavier. The thinning of the gate oxidation and the heavy doping of the a-Si and poly-Si with N-type or P-type carriers present a major challenge to the gate etch process.
Different doping types, doses, and activation level of the a-Si or poly-Si have a significant effect on the a-Si or poly-Si etch rate, as well as the etch profile. N-doped a-Si or poly-Si usually etches faster than P-doped a-Si or poly-Si in a plasma etch process. In adequately etching the P-type material, there is the possibility of etching the N-type material too much. In turn, any excessive etching may cause a localized breakthrough or xe2x80x9cmicro-trenchingxe2x80x9d of the thin gate oxidation in the bottom of the a-Si or poly-Si etch features.
In a typical a-Si or poly-Si gate plasma etching process, a main etch step with an optical endpoint is used to define the gate profile. The endpoint signal will trigger only when the a-Si or poly-Si begins clearing out of the wafer. At this point, there will be less N-doped a-Si remaining than P-doped Si. In addition, some N-doped a-Si may have been completely etched away. The etch process will break through the thin gate oxide and rapidly etch the underlying silicon substrate. After reaching the endpoint (or after the main-etch step) the process switches to a higher Si/SiO2 selectivity over-etch step and completely removes all of the remaining a-Si (or poly-Si). The selectivity of the over-etch step is much more than that of the main-etch step. This assures a reasonable gate profile.
With a relatively thin gate oxide, micro-trenching is problematic, especially in N-doped areas. In a plasma etch process, gate etch profile is also very sensitive to the doping of a-Si or poly-Si. In addition, the doping profiles between N-doped and P-doped a-Si or poly-Si may be different. Accordingly, there is a need to maintain a good gate etch profile that is substantially free of micro-trenching and provides a consistent gate etch profile between N-type and P-type doped gate stacks, as well as good critical dimension control as the process technology approaches fractional microns in feature sizes.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for forming a semiconductor device, including forming a first locally doped semiconductor region of a first conductivity type and a second locally doped semiconductor region of a second conductivity type over an undoped, lower semiconductor region. A first etch is implemented to simultaneously create a desired pattern in the first and second locally doped semiconductor regions in a manner that also provides a first passivation of exposed sidewalls of the first and second locally doped semiconductor regions, wherein the first etch removes material from the first and second locally doped semiconductor regions at a substantially constant rate with respect to one another, and in a substantially anisotropic manner. A second etch is implemented to complete the desired pattern in the undoped, lower semiconductor region in a manner that protects the first and second locally doped semiconductor regions from additional material removal therefrom.
In another aspect, a method for forming a semiconductor device includes forming a locally doped N-type polysilicon region and a locally doped P-type polysilicon region over an undoped, lower polysilicon region. A first etch is implemented to simultaneously create a gate conductor pattern in the locally doped N-type and P-type polysilicon regions in a manner that also provides a first passivation of exposed sidewalls of the locally doped N-type and P-type polysilicon regions, wherein said first etch removes material from said locally doped N-type and P-type polysilicon regions at a substantially constant rate with respect to one another, and in a substantially anisotropic manner. A second etch is implemented to complete the gate conductor pattern in the undoped, lower polysilicon region in a manner that protects the locally doped N-type and P-type polysilicon regions from additional material removal therefrom.